Master of Science (M.S.) Electrical Engineering

Illinois Institute of Technology, Chicago, IL, USA

May 2018

• Majored in VLSI and Microelectronics with a focus on CMOS circuit design, FPGA, SoC and RTL development along with dataflow modelling in Verilog. Used Cadence design tools for functional, logical and physical design and verification. 

• Final Project was design and analysis of a 32 bit pipelined MIPS RISC processor. The code was Verilog based and implementation was on ModelSim.

• IEEE, IIT chapter Project Chair

Bachelor of Engineering (B.E.) Electronics & Telecommunication

University of Pune, India

May 2016

• Majored in Embedded Systems with a focus on Hardware Development using processors like PIC, Arduino and 8051 to control interfaces and peripherals. 

• Final Project was a Dual Tone Multi Frequency based communication system in which we designed a remote door locking system using cellular network. A prototype model was developed by designing the circuit and developing the PCB and the mechanical enclosure of the product.